-------------------------------------------------------------------------------
-- Description: This is the testbench that instantiates the arithmetic unit and provides
-- the input signals. The outputs can be checked on the simulation waveforms.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity tb_ALU is
end tb_ALU;

architecture structural of tb_ALU is
component ALU
	port(rst         : in  std_logic;
		 counter_rst : in  std_logic;
		 A           : in  std_logic_vector(7 downto 0);
		 B           : in  std_logic_vector(7 downto 0);
		 FN          : in  STD_LOGIC_VECTOR(2 downto 0);
		 result      : out STD_LOGIC_VECTOR(7 downto 0);
		 overflow    : out STD_LOGIC;
		 sign        : out STD_LOGIC);
end component ALU;
	signal rst : std_logic;
	signal counter_rst : std_logic;
	signal FN       : std_logic_vector(2 downto 0);
	signal A        : std_logic_vector(7 downto 0);
	signal B        : std_logic_vector(7 downto 0);
	signal result   : std_logic_vector(7 downto 0);
	signal sign     : std_logic;
	signal overflow : std_logic;

	constant period : time := 25 ns;
	


begin                                   -- structural


	A <= "00000101",                    -- A = 5
		"00001001" after 1 * period,    -- A = 9 
		"00010001" after 2 * period,    -- A = 17  
		"10010001" after 3 * period,    -- A = 145  
		"10010100" after 4 * period,    -- A = 148  
		"11010101" after 5 * period,    -- A = 213  
		"00100011" after 6 * period,    -- A = 35  
		"11110010" after 7 * period,    -- A = 242  
		"00110001" after 8 * period,    -- A = 49  
		"01010101" after 9 * period;    -- A = 85  

	B <= "00000011",                    -- B = 3
		"00000011" after 1 * period,    -- B = 3 
		"10010001" after 2 * period,    -- B = 145
		"01111100" after 3 * period,    -- B = 124
		"11111001" after 4 * period,    -- B = 249
		"01101001" after 5 * period,    -- B = 105
		"00100011" after 6 * period,    -- B = 35
		"01101000" after 7 * period,    -- B = 104
		"00101101" after 8 * period,    -- B = 45
		"00100100" after 9 * period;    -- B = 36

	FN <= "000",                        -- Pass A
		"001" after 1 * period,         -- Pass B
		"000" after 2 * period,         -- Pass A
		"001" after 3 * period,         -- Pass B
		"010" after 4 * period,         -- Pass A + B
		"011" after 5 * period,         -- Pass A - B  
		"011" after 6 * period,         -- Pass A - B
		"010" after 7 * period,         -- Pass A + B
		"011" after 8 * period,         -- Pass A - B
		"100" after 9 * period;         -- Pass A + B

	DUT : ALU
		port map(
			rst		=> rst,
			counter_rst => counter_rst,
			A        => A,
			B        => B,
			FN       => FN,
			result   => result,
			sign     => sign,
			overflow => overflow
		);

end structural;
